Community Plugins#
Below is a list of other PeakRDL plugins created by community members.
If you’ve made your own plugin, feel free to share what you’ve built and we’ll add it to this list.
Test/Software Abstraction Layers#
Plugin |
Author |
Summary |
|---|---|---|
Generate a register abstraction layer for supported BEAM languages (Erlang and Elixir) from a SystemRDL definition. |
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A SystemRDL to raltest converter for cocotb |
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Generate an eUVM register model |
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Generate a C++ Hardware Abstraction Layer |
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Generate PSS (Portable test and Stimulus Standard) |
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Generate a Python Hardware Abstraction Layer |
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Simplified Python register abstraction layer exporter |
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Generate Rust code for accessing control/status registers |
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Exports TL-Verilog VIZ code for visualizing register blocks generated by PeakRDL-regblock |
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Generates raw address and size constants for SystemVerilog packages, C headers and linker scripts |
RTL Generators#
Plugin |
Author |
Summary |
|---|---|---|
Generate Bluespec SystemVerilog RTL |
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VHDL equivalent fork of PeakRDL-regblock |
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Simplified SystemVerilog generator |
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Generate OpenTitan register block SystemVerilog from SystemRDL files. |
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Verilog generator without structs, made explictly work with the icarus compiler |
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SystemVerilog Bus Decoder Generator from SystemRDL files. |
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Chisel generator. |
Documentation#
Plugin |
Author |
Summary |
|---|---|---|
Compile SystemRDL definitions into a Docx (MsWord) document |
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Generate Markdown documentation |
Format Converters#
Plugin |
Author |
Summary |
|---|---|---|
Convert to and from OpenTitan hjson format |
Editor Integrations#
Tool |
Author |
Summary |
|---|---|---|
VS Code extension and standalone LSP server for SystemRDL 2.0. Provides diagnostics, hover, goto-definition, references, CodeLens, inlay hints, and an interactive memory-map viewer. Built on systemrdl-compiler. Editor-agnostic LSP so other editors can adopt it. Also published on Open VSX. |